In order to increase memory capacity, manufacturers have continually moved memory chip or on-chip memory (such as flash memory) production to smaller process geometries over the last few years. Recently, multi-level signal memory cells have been used to increase flash memory capacity. In such an arrangement, a cell is configured to produce distinct signal threshold levels, which results in distinct read-back levels. With four level signals available per cell, two bits may be included into each flash memory cell. One problem with writing with four signal levels into each cell is that the distinction between adjacent levels may become difficult to discern. This is often referred to in the art as reduced signal distance (often shown as reduced Dmin). This may lead to a signal to noise ratio loss in the arrangement that needs to be recovered using error-control coding and signal processing.
When a multi-level data signal is obtained from a multi-level signal memory, there are various sources of noise that may corrupt the received signal and degrade the estimate of the bit value. It is critical for a signal processing or channel block to compensate for these noise effects and supply a code decoder with reliable inputs such that the net system performance is good.